Integrated circuits include many millions of gates that make up various functional components, such as flip-flops, multiplexers, and like type digital logic elements. Exemplary integrated circuits include application specific integrated circuits (ASICs), programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), and the like. A manufacturer may test logic elements in an integrated circuit using a scan chain of flip-flops. Each flip-flop in the scan chain is coupled to a logic element in logic under test. For a given input stimulus, the logic elements under test are expected to produce a particular output (“expected output”).
In a conventional scan chain, each flip-flop is switched back and forth between a capture mode and a scan cycle. During the capture mode, each flip-flop captures one bit of data from a logic element under test. During the scan cycle, the bits in the flip-flops are serially shifted out of the scan chain. The shifted-out bits are compared with the expected output values. The comparison results are used to validate functionality of the logic under test, as well as the integrated circuit. This technique has many disadvantages.
First, because the capture and scan modes are interlaced for each bit, it is not possible to perform bursts of high speed testing on the integrated circuit. Second, a conventional scan chain requires a separate control line for switching the flip-flops between capture and scan modes. The need to route this control signal to possibly thousands of flip-flops across the integrated circuit requires significant test circuit overhead. The term “test overhead” refers to resources required during testing and verification, but not required during actual operation of the logic under test. Reduction in test overhead is desirable, since a failure in a test resource may disqualify an integrated circuit part, even if the resources intended for use by a customer are fully functional. Accordingly, there exists a need in the art for a more efficient scan chain structure for functional verification and testing of integrated circuits.